There has been increasingly a demand for nonvolatile storage devices including rewritable nonvolatile memories, mainly for semiconductor memory cards, as external recording devices for use with non-real-time recording apparatuses as represented by personal computers (PCs) and real-time recording apparatuses as represented by digital video cameras. There are various types of semiconductor memory cards, and one type of such semiconductor memory cards are SD (secure digital (trademark)) memory cards.
Such an SD memory card includes a flash memory which is a nonvolatile memory and a memory controller for controlling the flash memory. The memory controller controls reading and writing from and to the flash memory, in response to commands for reading and writing from an access apparatus such as a PC.
Consideration is now made for a case where such an SD card is loaded to an access apparatus such as a PC such that the SD card is regarded as a removable disk with respect to the access apparatus and is managed with a FAT file system for accessing data thereto. With the FAT system, in recording files or data to the recording device, data is read and written usually on a cluster-by-cluster basis, using a file allocation table (FAT).
A flash memory for use as a main storage memory in a semiconductor memory card includes plural physical blocks as units of erasure, each physical block including pages as units of writing. The semiconductor memory card employing such a flash memory has a specific problem of the restriction on the number of times data can be rewritten therein. Although improvement has been made through novel memory techniques, such semiconductor memory cards are not perfect in terms of the reliability for storage of data, in cases of using the semiconductor memory cards as external storage devices. Therefore, there is a need for managing the reliability of data in such a semiconductor memory card, as well as reading and writing of data.
In general, replacement blocks are prepared in a semiconductor memory card, and a bad block which induces read/writ errors is replaced by the replacement block, in order to improve the reliability. Also, in order to prevent concentration of rewriting of data on a certain physical block, an address management method such as wear leveling has been employed. The wear leveling is a so-called logical-to-physical address conversion technique for converting a logical address specified by an access apparatus into a physical address in a flash memory and is generally realized with an address management table.
As one wear leveling method, a dispersion-type address management method has been conventionally employed. The dispersion-type address management method is a method which pre-stores, in management areas of pages as units of writing, logical addresses and status flags of the corresponding blocks and, at the time of initialization, reads the pre-stored information and creates an address management table in a RAM in a memory controller on the basis of the read information.
However, in cases of a nonvolatile storage device having a large-capacity memory space, the aforementioned wear leveling method requires an extremely long time period for reading the management areas in the entire memory space, at the time of initialization. This may violate specifications, for example, in such a way as to cause initialization time to exceed upper limit in the specification of initialization time of the nonvolatile storage device to be exceeded. Also, even in cases of a nonvolatile storage device having no particular specifications, the aforementioned wear leveling method causes the demerit of the increase of the waiting time until the nonvolatile storage device becomes accessible, even through this does not violate specifications. Furthermore, the RAM which temporarily stores the address management table is required to have an extremely large capacity, thereby causing a problem in the cost.
In order to overcome the aforementioned problem, storage devices as described in Patent Document 1, (i.e, JP-A-2003-323352) employ a combination of two techniques which are (1) a segment management method and (2) a concentration-type address management method.
The segment management method is a method which divides an entire logical address space to be managed by an access apparatus into plural logical address ranges (regions) and manages the plural logical address ranges in association with plural physical areas (segments) in a flash memory which are created by physically dividing the flash memory.
On the other hand, the concentration-type address management method is a method which pre-stores an address management table itself in a flash memory, reads the address management table in a RAM in response to each data writing command from an access apparatus and updates the address management table in the RAM and rewrites it to the flash memory after the completion of the writing of data.    Patent Document 1: JP-A-2003-323352